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1 white electronic designs corporation ? (602) 437-1520 www.whiteedc.com edi9lc644v january 2002 rev. 4 eco# 14667 description the edi9lc644vxxbc is a 3.3v, 128k x 32 synchronous pipeline sram and a 1mx32 synchronous dram array con- structed with one 128k x 32 sbsram and two 1mx16 sdram die mounted on a multilayer laminate substrate. the device is packaged in a 153 lead, 14mm by 22mm, bga. the edi9lc644vxxbc provides a total memory solution for the texas instruments tms320c6201 and the tms320c6701 dsps the synchronous pipeline sram is available with clock speeds of 200, 166,150, and 133 mhz, allowing the user to develop a fast external memory for the ssram inter- face port . the sdram is available in clock speeds of 125 and 100 mhz, allowing the user to develop a fast external memory for the sdram interface port . 128kx32 ssram/1mx32 sdram

features clock speeds: ssram: 200, 166,150, and 133 mhz sdrams: 125 and 100 mhz dsp memory solution texas instruments tms320c6201 texas instruments tms320c6701 packaging: 153 pin bga, jedec mo-163 3.3v operating supply voltage direct control interface to both the ssram and sdram ports on the ?c6x? common address and databus 65% space savings vs. monolithic solution reduced system inductance and capacitance fig. 1 pin configuration 12 3456 789 a dq 19 dq 23 v cc v ss v ss v ss v cc dq 24 dq 28 a b dq 18 dq 22 v cc v ss sdce v ss v cc dq 25 dq 29 b c v ccq v ccq v cc sdwe sda 10 nc v cc v ccq v ccq c d dq 17 dq 21 v cc v ss v ss v ss v cc dq 26 dq 30 d e dq 16 dq 20 v cc v ss sdclk v ss v cc dq 27 dq 31 e f v ccq v ccq v cc v ss v ss v ss v cc v ccq v ccq f g nc nc nc sdras sdcas v ss a 2 a 4 a 5 g h nc nc a 8 v ss v ss nc a 1 a 3 a 10 h j a6 a7 a9 vss vss nc a0 a11 a12 j k nc/a 17 nc/a 18 nc/a 19 v ss v ss nc nc a 13 a 14 k l nc nc nc bwe 2 bwe 3 nc nc a 15 a 16 l m v ccq v ccq v cc bwe 0 bwe 1 nc v cc v ccq v ccq m n dq 12 dq 11 v cc v ss v ss v ss v cc dq 4 dq 0 n p dq 13 dq 10 v cc v ss ssclk v ss v cc dq 5 dq 1 p r v ccq v ccq v cc v ss v ss v ss v cc v ccq v ccq r t dq 14 dq 9 v cc ssadc sswe nc v cc dq 6 dq 2 t u dq 15 dq 8 v cc ssoe ssce nc v cc dq 7 dq 3 u 12 3456 789 bottom view a 0-16 address bus dq 0-31 data bus ssclk ssram clock ssadc ssram address status control sswe ssram write enable ssoe ssram output enable sdclk sdram clock sdras sdram row address strobe sdcas sdram column address strobe sdwe sdram write enable sda 10 sdram address 10/auto precharge bwe 0-3 ssram byte write enables sdram sdqm 0 - 3 ssce chip enable ssram device sdce chip enable sdram device v cc power supply pins, 3.3v v ccq data bus power supply pins, 3.3v (2.5v future) v ss ground nc no connect p in d escription
2 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v

3 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v output functional descriptions symbol type signal polarity function ssclk input pulse positive edge the system clock input. all of the ssram inputs are sampled on the rising edge of the clock. ssads when sampled at the positive rising edge of the clock, ssads, ssoe, and sswe define the operation ssoe input pulse active low to be executed by the ssram. sswe ssce input pulse active low ssce disable or enable ssram device operation. sdclk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. sdce input pulse active low sdce disable or enable device operation by masking or enabling all inputs except sdclk and bwe0-3. sdras when sampled at the positive rising edge of the clock, sdcas, sdras, and sdwe define the sdcas input pulse active low operation to be executed by the sdram. sdwe address bus for ssram and sdram a 0 and a 1 are the burst address inputs for the ssram during a bank active command cycle, a 0-9 , sda 10 defines the row address (ra 0-10 ) when sampled at the rising clock edge. a 0-16 , input level ? during a read or write command cycle, a 0-7 defines the column address (ca 0-7 ) when sampled at sda 10 the rising clock edge. in addition to the row address, sda 10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. if sda 10 is high, autoprecharge is selected and a 11 defines the bank to be precharged (low = bank a, high = bank b). if sda 10 is low, autoprecharge is disabled. during a precharge command cycle, sda 10 is used in conjunction with a 11 to control which bank(s) to precharge. if sda 10 is high, both bank a and bank b will be precharged regardless of the state of a 11 . if sda 10 is low, then a 11 is used to define which bank to precharge. dq 0-31 input level ? data input/output are multiplexed on the same pins. output bwe 0-3 input pulse bwe 0-3 perform the byte write enable function for the ssram and dqm function for the sdram. bwe 0 is associated with dq 0-7 , bwe 1 with dq 8-15 , bwe 2 with dq 16-23 and bwe 3 with dq 24-31 . v cc , v ss supply power and ground for the input buffers and the core logic. v ccq supply data base power supply pins, 3.3v (2.5v future).
4 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v recommended dc operating conditions (0c - t a - 70c; v cc = 3.3v -5% / +10% unless otherwise noted ) absolute maximum ratings *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.

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+ % & # parameter symbol min max units supply voltage 1 v cc 3.135 3.6 v input high voltage 1,2 v ih 2.0 v cc +0.3 v input low voltage 1,2 v il -0.3 0.8 v input leakage current il i -10 10 a 0 - v in - vcc output leakage (output disabled) il o -10 10 a 0 - v in - vcc output high (i oh = -4ma) 1 v oh 2.4 ? v output low (i ol = 8ma) 1 v ol ? 0.4 v notes: 1. all voltages referenced to vss (gnd). 2. overshoot: v ih +6.0v for t - t kc /2 underershoot: v il 3 -2.0v for t - t kc /2 dc electrical characteristics description conditions symbol frequency typ max units power supply current: 133mhz 400 550 operating (1,2,3) ssram active / dram auto refresh i cc 1 150mhz 450 580 ma 166mhz 500 625 200mhz tbd tbd power supply current 133mhz 300 450 operating 1,2,3 ssram active / dram idle i cc 2 150mhz 350 480 ma 166mhz 400 525 200mhz tbd tbd power supply current 83mhz 220 240 operating 1,2,3 sdram active / ssram idle i cc 3 100mhz 235 250 ma 125mhz 255 280 ssce and sdce v cc -0.2v, i sb 1 20.0 40.0 cmos standby all other inputs at v ss +0.2 v in or ma v in v cc -0.2v, clk frequency = 0 ssce and sdce v ih min i sb 2 30.0 55.0 ttl standby all other inputs at v il max v in or ma v in v cc -0.2v, clk frequency = 0 auto refresh i cc 5 190 250 ma notes: 1. i cc (operating) is specified with no output current. i cc (operating) increases with faster cycle times and greater output loading. 2. ?device idle? means device is deselected (ce 3 v ih ) clock is running at max frequency and addresses are switching each cycle. 3. typical values are measured at 3.3v, 25c. i cc (operating) is specified at specified frequency. description conditions symbol typ max units address input capacitance 1 t a = 25c; f = 1mhz c i 58 pf input/output capacitance (dq) 1 t a = 25c; f = 1mhz c o 810pf control input capacitance 1 t a = 25c; f = 1mhz c a 58 pf clock input capacitance 1 t a = 25c; f = 1mhz c ck 46 pf note: 1. this parameter is sampled. bga capacitance
5 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v ssram ac characteristics (edi9lc644v) symbol 200mhz 166mhz 150mhz 133mhz parameter min max min max min max min max units clock cycle time t khkh 5678ns clock high time t klkh 1.6 2.4 2.6 2.8 ns clock low time t khkl 1.6 2.4 2.6 2.8 ns clock to output valid t khqv 2.5 3.5 3.8 4.0 ns clock to output invalid t khqx 1.5 1.5 1.5 1.5 ns clock to output on low-z t kqlz 0000ns clock to output in high-z t kqhz 1.5 3 1.5 3.5 1.5 3.8 1.5 4.0 ns output enable to output valid t oelqv 2.5 3.5 3.8 4.0 ns output enable to output in low-z t oelz 0000ns output enable to output in high-z t oehz 3.0 3.5 3.5 3.8 ns address, control, data-in setup time to clock t s 1.5 1.5 1.5 1.5 ns address, control, data-in hold time to clock t h 0.5 0.5 0.5 0.5 ns operation address used ssce ssads sswe ssoe dq deselected cycle, power down none h l x x high-z write cycle, begin burst external l l l x d read cycle, begin burst external l l h l q read cycle, begin burst external l l h h high-z read cycle, suspend burst current x h h l q read cycle, suspend burst current x h h h high-z read cycle, suspend burst current h h h l q read cycle, suspend burst current h h h h high-z write cycle, suspend burst current x h l x d write cycle, suspend burst current h h l x d note: 1. x means ?don?t care?, h means logic high. l means logic low. 2. all inputs except ssoe must meet setup and hold times around the rising edge (low to high) of ssclk. 3. suspending burst generates wait cycle 4. for a write operation following a read operation, ssoe must be high before the input data required setup time plus high-z ti me for ssoe and staying high though out the input data hold time. 5. this device contains circuitry that will ensure the outputs will be in high-z during power-up. ssram operation truth table ssram partial truth table function sswe bwe0 bwe1 bwe2 bwe3 read h x x x x write one byte (dq 0-7 )llhhh write all bytes l l l l l
6 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v fig. 3 ssram read timing fig. 4 ssram write timing
7 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v sdram ac characteristics symbol 125mhz 100mhz 83mhz parameter min max min max min max units clock cycle time 1 cl = 3 t cc 8 1000 10 1000 12 1000 ns cl = 2 t cc 10 1000 12 1000 15 1000 clock to valid output delay 1,2 t sac 678ns output data hold time 2 t oh 33 3ns clock high pulse width 3 t ch 33 3ns clock low pulse width 3 t cl 33 3ns input setup time 3 t ss 22 2ns input hold time 3 t sh 11 1ns clk to output low-z 2 t slz 22 2ns clk to output high-z t shz 778ns row active to row active delay 4 t rrd 20 20 24 ns ras to cas delay 4 t rcd 20 20 24 ns row precharge time 4 t rp 20 20 24 ns row active time 4 t ras 50 10,000 50 10,000 60 10,000 ns row cycle time - operation 4 t rc 70 80 90 ns row cycle time - auto refresh 4,8 t rfc 70 80 90 ns last data in to new column address delay 5 t cdl 1 1 1 clk last data in to row precharge 5 t rdl 1 1 1 clk last data in to burst stop 5 t bdl 1 1 1 clk column address to column address delay 6 t ccd 1.5 1.5 1.5 clk number of valid output data 7 22 2 12 1 ea notes: 1. parameters depend on programmed cas latency. 2. if clock rise time is longer than 1ns (t rise /2 -0.5)ns should be added to the parameter. 3. assumed input rise and fall time = 1ns. if t rise of t fall are longer than 1ns. [(t rise = t fall )/2] - 1ns should be added to the parameter. 4. the minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and t hen rounding up to the next higher integer. 5. minimum delay is required to complete write. 6. all devices allow every cycle column address changes. 7. in case of row precharge interrupt, auto precharge and read burst stop. 8. a new command may be given t rfc after self-refresh exit.
8 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v clock frequency and latency parameters - 125mhz sdram (u nit = number of clock ) frequency cas t rc t ras t rp t rrd t rcd t ccd t cdl t rdl latency 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 125mhz (8.0ns) 3 9 6 3 2 3 1 1 1 100mhz (10.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 4 2 2 2 1 1 1 clock frequency and latency parameters - 100mhz sdram (u nit = number of clock ) frequency cas t rc t ras t rp t rrd t rcd t ccd t cdl t rdl latency 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100mhz (12.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 5 2 2 2 1 1 1 -10 -12 parameter symbol min max min max units refresh period 1,2 t ref ?64 ? 64 ms notes: 1. 4096 cycles 2. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to ?wake-up? the device. refresh cycle parameters mode register set l l l l x op code auto refresh (cbr) l l l h x x x precharge single bank l l h l x ba l 2 precharge all banks l l h l x x h bank activate l l h h x ba row address 2 write l h l l x ba l 2 write with auto precharge l h l l x ba h 2 read l h l l x ba l 2 read with auto precharge l h l h x ba h 2 burst termination l h h l x x x 3 no operation l h h h x x x device deselect h x x x x x x data write/output disable x x x x l x x 4 data mask/output disable x x x x h x x 4 function sdce sdras sdcas sdwe bwe a 11 sda 10 notes a 9-0 sdram command truth table notes: 1. all of the sdram operations are defined by states of sdce, sdwe, sdras, sdcas, and bwe 0-3 at the positive rising edge of the clock. 2. bank select (ba), if a 11 = 0 then bank a is selected, if ba = 1 then bank b is selected. 3. during a burst write cycle there is a zero clock delay, for a burst read cycle the delay is equal to the cas latency. 4. the bwe has two functions for the data dq read and write operations. during a read cycle, when bwe goes high at a clock timi ng the data outputs are disabled and become high impedance after a two clock delay. bwe also provides a data mask function for write cycles. when it ac tivates, the write operation at the clock is prohibited (zero clock latency).
9 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v l l l l op code mode register set set the mode register 1 l l l h x x auto or self refresh start auto 1 l l h l x x precharge no operation l l h h ba row address bank activate activate the specified bank and row idle l h l l ba column write w/o precharge illegal 2 l h l h ba column read w/o precharge illegal 1 l h h l x x burst termination no operation 1 l h h h x x no operation no operation h x x x x x device deselect no operation l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge precharge 3 l l h h ba row address bank activate illegal 1 row active l h l l ba column write s tart write; determine if auto precharge 4,5 l h l h ba column read start read; determine if auto precharge 4,5 l h h l x x burst termination no operation l h h h x x no operation no operation h x x x x x device deselect no operation l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate illegal 2 read l h l l ba column write terminate burst; start the write cycle 5,6 l h l h ba column read terminate burst; start a new read cycle 5,6 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate illegal 2 write l h l l ba column write terminate burst; start a new write cycle 5,6 l h l h ba column read terminate burst; start the read cycle 5,6 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 2 read with l l h h ba row address bank activate illegal 2 auto precharge l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst sdram current state truth table current state command action notes sdce sdras sdcas sdwe a 11 sda 10 -a 0 description (ba)
10 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 2 write with l l h h ba row address bank activate illegal 2 auto precharge l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge no operation; bank(s) idle after trp l l h h ba row address bank activate illegal 2 precharging l h l l ba column write w/o precharge illegal 2 l h l h ba column read w/o precharge illegal 2 l h h l x x burst termination no operation; bank(s) idle after trp l h h h x x no operation no operation; bank(s) idle after trp h x x x x x device deselect no operation; bank(s) idle after trp l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 2 l l h h ba row address bank activate illegal 2 row activating l h l l ba column write illegal 2 l h l h ba column read illegal 2 l h h l x x burst termination no operation; row active after trcd l h h h x x no operation no operation; row active after trcd h x x x x x device deselect no operation; row active after trcd l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 2 l l h h ba row address bank activate illegal 2 write recovering l h l l ba column write start write; determine if auto precharge 6 l h l h ba column read start read; determine if auto precharge 6 l h h l x x burst termination no operation; row active after tdpl l h h h x x no operation no operation; row active after tdpl h x x x x x device deselect no operation; row active after tdpl l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 2 write recovering l l h h ba row address bank activate illegal 2 with auto l h l l ba column write illegal 2,6 precharge l h l h ba column read illegal 2,6 l h h l x x burst termination no operation; precharge after tdpl l h h h x x no operation no operation; precharge after tdpl h x x x x x device deselect no operation; precharge after tdpl sdram current state truth table (cont.) current state command action notes sdce sdras sdcas sdwe a 11 sda 10 -a 0 description (ba)
11 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v notes: 1. both banks must be idle otherwise it is an illegal action. 2. the current state refers only refers to one of the banks, if ba selects this bank then the action is illegal. if ba selects the bank not being referenced by the current state then the action may be legal depending on the state of that bank. 3. the minimum and maximum active time (t ras ) must be satisfied. 4. the ras to cas delay (t rcd ) must occur before the command is given. 5. address sda10 is used to determine if the auto precharge function is activated. 6. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied. l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal l l h h ba row address bank activate illegal refreshing l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination no operation; idle after trc l h h h x x no operation no operation; idle after trc h x x x x x device deselect no operation; idle after trc l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal mode register l l h h ba row address bank activate illegal accessing l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation no operation; idle after two clock cycles h x x x x x device deselect no operation; idle after two clock cycles current state command action notes sdce sdras sdcas sdwe a 11 sda 10 -a 0 description (ba) sdram current state truth table (cont.)
12 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v fig. 5 sdram single bit read-write-read cycle (same page) @ cas latency = 3, burst length = 1
13 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v fig. 6 sdram power up sequence
14 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v fig. 7 sdram read & write cycle at same bank @ burst length = 4 notes: 1. minimum row cycle times are required to complete internal dram operation. 2 row precharge can interrupt burst on any cycle. (cas latency - 1) number of valid output data is available after row precharg e. last valid output will be hi-z (t shz ) after the clock. 3. access time from row active command. t cc *(t rcd + cas latency - 1) + t sac . 4. output will be hi-z after the end of burst. (1, 2, 4, 8 & full page bit burst)
15 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v fig. 8 sdram page read & write cycle at same bank @ burst length = 4 notes: 1. to write data before burst read ends. bwe should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge will be written. 3. bwe should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally.
16 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v fig. 9 sdram page read cycle at different bank @ burst length = 4 notes: 1. sdce can be ?don?t care? when sdras, sdcas and sdwe are high at the clock going high edge. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
17 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v fig. 10 sdram page write cycle at different bank @ burst length = 4 notes: 1. to interrupt burst write by row precharge, bwe should be asserted to mask invalid input data. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
18 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v fig. 11 sdram read & write cycle at different bank @ burst length = 4 notes: 1. t cdl should be met to complete write.
19 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v fig. 12 sdram read & write cycle with auto precharge @ burst length = 4 notes: 1. t cdl should be controlled to meet minimum t ras before internal precharge start. (in the case of burst length = 1 & 2 and brsw mode)
20 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v fig. 13 sdram read interrupted by precharge command & read burst stop @ burst length = full page notes: 1. at full page mode, burst is end at the end of burst. so auto precharge is possible. 2. about the valid dqs after burst stop, it is the same as the case of sdras interrupt. both cases are illustrated in the above timing diagram. see the label 1, 2 on each of them. but at burst write, burst stop and sdras interrupt should be compared carefully. refer to the timing diagram of ? full page write burst stop cycle ? . 3. burst stop is valid at every burst length.
21 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v fig. 14 sdram write interrupted by precharge command & write burst stop @ burst length = full page notes: 1. at full page mode, burst is end at the end of burst. so auto precharge is possible. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl . bwe at write interrupt by precharge command is needed to prevent invalid write. bwe should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data afte r row precharge cycle will be masked internally. 3. burst stop is valid at every burst length.
22 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v fig. 15 sdram burst read single bit write cycle @ burst length = 2 notes: 1. brsw modes enabled by setting a 9 ? high ? at mrs (mode register set). at the brsw mode, the burst length at write is fixed to ? 1 ? regardless of programmed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command, the next cycle starts the precharge.
23 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v fig. 16 sdram mode register set cycle *both banks precharge should be completed before mode register set cycle and auto refresh cycle. notes: mode register set cycle 1. sdce, sdras, sdcas & sdwe activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new sdras activation. 7. please refer to mode register set table. sdram auto refresh cycle high
24 white electronic designs corporation phoenix az (602) 437-1520 edi9lc644v package description: 153 lead bga (17 x 9 ball array)
part number ssram access sdram access edi9lc644v2012bc 200mhz 125mhz edi9lc644v2010bc 200mhz 100mhz edi9lc644v1612bc 166mhz 125mhz edi9lc644v1610bc 166mhz 100mhz edi9lc644v1512bc 150mhz 125mhz edi9lc644v1510bc 150mhz 100mhz EDI9LC644V1312BC 133mhz 125mhz edi9lc644v1310bc 133mhz 100mhz ordering information all linear dimensions are millimeters and parenthetically in inches note: ball attach pad for above bga is 480 microns, in diameter. pad is solder mask defined.
25 white electronic designs corporation (602) 437-1520 www.whiteedc.com edi9lc644v fig. 17 interfacing the texas instruments tms320c6 x with the ed9lc644v (128k x 32 ssram/1m x 32 sdram) a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 sswe\ ssce\ ssoe\ ssadc\ ssclk bwe 0 \ bwe 1 \ bwe 2 \ bwe 3 \ sda 10 sdce\ sdras\ sdcas\ sdwe\ sdclk sswe\ ce 2 \ ssoe\ ssads\ ssclk be 0 \ be 1 \ be 2 \ be 3 \ sda 10 ce 0 \ sdras\ sdcas\ sdwe\ sdclk dq 0-7 dq 8-15 dq 16-23 dq 24-31 address bus ea 2-21 data bus ed 0-31 texas instruments tms320c6x dsp edi9lc644v 128k x 32 ssram 1m x 32 sdram ssram control sdram control shared controls ea 2 ea 3

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